When I was a child, watching various sci-fi movies, I was dreaming of how matter would be organized on those blocky crystals they showed off as storage for endless quantities of information. Well, it seems we’re getting there now:
Rice University scientists have created the first two-terminal memory chips that use only silicon, one of the most common substances on the planet, in a way that should be easily adaptable to nanoelectronic manufacturing techniques and promises to extend the limits of miniaturization subject to Moore’s Law.
Last year, researchers in the lab of Rice Professor James Tour showed how electrical current could repeatedly break and reconnect 10-nanometer strips of graphite, a form of carbon, to create a robust, reliable memory “bit.” At the time, they didn’t fully understand why it worked so well.
Now, they do. A new collaboration by the Rice labs of professors Tour, Douglas Natelson and Lin Zhong proved the circuit doesn’t need the carbon at all.
Jun Yao, a graduate student in Tour’s lab and primary author of the paper that appears today in the online edition of Nano Letters, confirmed his breakthrough idea when he sandwiched a layer of silicon oxide, an insulator, between semiconducting sheets of polycrystalline silicon that served as the top and bottom electrodes.
Applying a charge to the electrodes created a conductive pathway by stripping oxygen atoms from the silicon oxide and forming a chain of nano-sized silicon crystals. Once formed, the chain can be repeatedly broken and reconnected by applying a pulse of varying voltage.
The nanocrystal wires are as small as 5 nanometers (billionths of a meter) wide, far smaller than circuitry in even the most advanced computers and electronic devices.
“The beauty of it is its simplicity,” said Tour, Rice’s T.T. and W.F. Chao Chair in Chemistry as well as a professor of mechanical engineering and materials science and of computer science. That, he said, will be key to the technology’s scalability. Silicon oxide switches or memory locations require only two terminals, not three (as in flash memory), because the physical process doesn’t require the device to hold a charge.
It also means layers of silicon-oxide memory can be stacked in tiny but capacious three-dimensional arrays. “I’ve been told by industry that if you’re not in the 3-D memory business in four years, you’re not going to be in the memory business. This is perfectly suited for that,” Tour said.
Silicon-oxide memories are compatible with conventional transistor manufacturing technology, said Tour, who recently attended a workshop by the National Science Foundation and IBM on breaking the barriers to Moore’s Law, which states the number of devices on a circuit doubles every 18 to 24 months.
“Manufacturers feel they can get pathways down to 10 nanometers. Flash memory is going to hit a brick wall at about 20 nanometers. But how do we get beyond that? Well, our technique is perfectly suited for sub-10-nanometer circuits,” he said.
